The present invention pertains to the field design-for-testability of integrated circuit devices. More particularly, the present invention relates to a method and system for preventing bus contention within an integrated circuit device during internal scan testing.
Computer systems, software applications, and the devices and processes built around them are continually growing in power and complexity. Society""s reliance on such systems is likewise increasing, making it critical that the systems obey the properties their designers intended. Typically, the more powerful and complex the system, the greater its utility and usefulness. However, as these computer and software implemented systems and processes become more powerful, detecting and correcting flaws within the systems becomes increasingly difficult.
As integrated circuits, and particularly the logic portion of integrated circuits, have become more complex and more dense, they have become progressively harder to test in order to ensure correct and complete functionality. For example, with current technology, as the total number of transistors fabricated within an integrate circuit die increases, the amount of time which the integrated circuit emerging from a fabrication process line spends in testing increases as well. Hence, the testing cost can be very significant for the latest and largest high density integrated circuits. Very sophisticated test programs, automatic test pattern generation (ATPG) programs, are used to analyze the various netlists representative of the integrated circuit designs and generate therefrom the test patterns (e.g., also referred to as test programs or test vectors) used for testing the devices in automated test equipment (ATE) systems.
The objective of the ATPG program, or tool, is to generate an accurate, high coverage (e.g., testing most of the embodying circuitry of the integrated circuit) test pattern as efficiently as possible, to reduce the cost. Thus, an increasingly important part of the logic synthesis process involves designing ASICs and other complex integrated circuits for inherent testability. This is referred to as designing for testability, or DFT.
One problematic aspect of the DFT process involves high density, multifunction integrated circuits incorporating multiple functional units on one or more internal busses. The use of internal three-state signals or busses with multiple drivers has become commonplace in state-of-the-art system-on-a-chip designs. Also commonplace is the usage of internal scan testing methodologies to test complex designs. Generally, these two aspects of state-of-the-art design have contradictory design and testing impacts to one another.
Current ATPG tools have difficulty interpreting and controlling such structures, but nevertheless require that one and only one driver be actively driving a shared signal at any given time. Multiple active drivers can produce unexpected test results and can potentially damage components during manufacturing test. This problem is made more difficult to solve when the multiple drivers are independently controlled from unique functional blocks that contain autonomous circuitry to activate their respective bus drivers.
One prior art solution for dealing with the problem of multiple functional units contending for one or more internal busses is the implementation of a methodology of forcing the ATPG tool to resolve all bus contention issues. However, this results in lower fault coverage and physically longer times to generate patterns. Additionally, many ATPG programs and tools do not support this solution.
Additionally, the tools that do support bus contention resolution and prevention only do this with limited success. They guarantee that ATPG patterns will not be generated that cause bus contention on any signals or busses, but it is often difficult for the tools to do. The result is often extremely long compile times and very poor fault coverage.
Thus, what is required is a solution that is capable of eliminating any potential bus contention among multiple functional units of an integrated circuit device. What is required is a solution that actively controls multiple bus drivers for the multiple functional units to eliminate bus contention. The required solution should guarantee by design that bus contention cannot occur given any scan test pattern that an ATPG tool might generate, and thus produce test patterns that will result in much higher fault coverage and much faster compile times. The required solution should be easy to implement, uniform in construction and have minimal gate area and system performance impacts on the design.
The present invention is a method and system for eliminating any potential bus contention among multiple functional units of an integrated circuit device. The present invention provides a solution that actively controls multiple bus drivers for the multiple functional units to eliminate bus contention among the functional units as they are stimulated by a series of test inputs (e.g., ATPG test patterns, vectors, etc.). The method and system of the present invention guarantees by design that bus contention cannot occur given any scan test pattern that an ATPG tool might generate, thus allowing the ATPG tool to produce test patterns that will result in much higher fault coverage. Additionally, since the ATPG tool would not have to ensure bus contention could not occur, test patterns can be generated with much faster compile times. The system of the present invention is easily implemented, uniform in construction, and has minimal gate area and system performance impacts on the overall design of integrated circuit devices.
In one embodiment, the present invention is implemented as a system for preventing bus contention in a multifunction integrated circuit as the circuit undergoes testing. The system is implemented in an integrated circuit adapted to accept a series of test inputs operable for testing the functionality of the integrated circuit. The integrated circuit includes at least one bus for communicatively coupling the multiple functions. At least a first functional block and a second functional block are included in the integrated circuit. The first functional block and the second functional block are both coupled to the bus (e.g., a PCI bus) and coupled to accept the test inputs from an externally coupled ATE device. A series of output enable controllers are also included in the integrated circuit. The output enable controllers are coupled to both functional blocks and are operable to disable the output drivers of the second functional block if a corresponding output of the first functional block is activated. This guarantees that the test inputs can propagate through the first functional block and the second functional block, and any other lower priority blocks, without causing contention for the bus.